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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSC7116 датащи(PDF) 29 Page - Freescale Semiconductor, Inc |
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MSC7116 датащи(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 60 page  Electrical Characteristics MSC7116 Data Sheet, Rev. 13 Freescale Semiconductor 29 2.5.6 Ethernet Timing 2.5.6.1 Receive Signal Timing Figure 9. TDM Transmit Signals Table 21. Receive Signal Timing No. Characteristics Min Max Unit 800 Receive clock period: • MII: RXCLK (max frequency = 25 MHz) • RMII: REFCLK (max frequency = 50 MHz) 40 20 — — ns ns 801 Receive clock pulse width high—as a percent of clock period • MII: RXCLK • RMII: REFCLK 35 14 7 65 — — % ns ns 802 Receive clock pulse width low—as a percent of clock period: • MII: RXCLK • RMII: REFCLK 35 14 7 65 — — % ns ns 803 RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time 4 — ns 804 Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time 2 — ns Figure 10. Ethernet Receive Signal Timing TDMxTCK TDMxTD 306 307 309 308 300 301 302 311 310 TDMxRCK TDMxTFS (output) TDMxTFS (input) 303 305 Valid Receive RX_DV RXDn RX_ER 803 804 clock 800 802 801 CRS_DV |
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