MCF52235 datasheet(8/54 Pages) FREESCALE

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MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7

MCF52235 Family Configurations

Freescale Semiconductor

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low power modes

•

DMA controller

— Four fully programmable channels

— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 x 32-bit)

burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

•

Reset

— Separate reset in and reset out signals

— Seven sources of reset:

–

Power-on reset (POR)

–

External

–Software

–

Watchdog

–

Loss of clock

–

Loss of lock

–

Low-voltage detection (LVD)

— Status flag indication of source of last reset

•

Chip integration module (CIM)

— System configuration during reset

— Selects one of three clock modes

— Configures output pad drive strength

— Unique part identification number and part revision number

•

General purpose I/O interface

— Up to 56 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Programmable drive strengths

— Unused peripheral pins may be used as extra GPIO

•

JTAG support for system level board testing

1.2.2

V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage

instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is

a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).

The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage

(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack

pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235 core includes the enhanced

multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic

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