MCF52235 datasheet(21/54 Pages) FREESCALE

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UART 13

UCTS1

SYNCA

URXD2

PUB[3]

PDSR[15]

—

URTS1

SYNCB

UTXD2

PUB[2]

PDSR[14]

—

URXD1

—

FEC_TXD[0]

PUB[1]

PDSR[13]

PWOR[2]

—

UTXD1

—

FEC_COL

PUB[0]

PDSR[12]

PWOR[3]

—

UART 2

UCTS2

—

PUC[3]

PDSR[27]

—

L10

—

URTS2

—

PUC[2]

PDSR[26]

—

K10

—

URXD2

—

PUC[1]

PDSR[25]

—

K11

—

UTXD2

—

PUC[0]

PDSR[24]

—

L11

—

FlexCAN

SYNCA

CANTX4

FEC_MDIO

PAS[3]

PDSR[39]

—

SYNCB

CANRX4

FEC_MDC

PAS[2]

PDSR[39]

—

VDD5,11

VDD

—

N/A

—

D7, E8

65,102

45,74

VDDX

—

N/A

—

D5, D6, E6, G5,

G6, G7, H6

14, 43

10, 31

VSS

—

N/A

—

E4, E5, E7,F4,

F5, F6, F7, F8

64,101

44,73

VSSX

—

N/A

—

15, 42

11, 30

1 The PDSR and PSSR registers are described in Chapter 14, “General Purpose I/O Module. All programmable signals default to 2mA drive in normal

(single-chip) mode.

2 All signals have a pull-up in GPIO mode.

3 The use of an external PHY limits ADC, interrupt, and QSPI functionality. It also disables the UART0/1 and timer pins.

4 The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.

5 The VDD1, VDD2, VDDPLL, and PHY_VDD pins are for decoupling only and should not have power directly applied to them.

6 For primary and GPIO functions only.

7 Only when JTAG mode is enabled.

8 For secondary and GPIO functions only.

9 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended.

10 For GPIO function. Primary Function has pull-up control within the GPT module.

11 This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY.

Table 3. Pin Functions by Primary and Alternate Purpose (continued)

Pin Group

Primary

Function

SecondaryF

unction

Tertiary

Function

Quaternary

Function

Drive

Strength/

Control1

Wired OR

Control

Pull-up/

Pull-down2

Pin on 121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

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