33291L datasheet(9/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33291L

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

Figure 4. Valid Data Delay Time and

Valid Time Test Circuit

Figure 5. Enable and Disable Time Test Circuit

Figure 6. Valid Data Delay Time and

Valid Time Waveforms

Figure 7. Enable and Disable Time Waveforms

VDD = 5.0 V

SCLK

CL = 200 pF

33291L

Under

Test

CL represents the total capacitance of the test fixture and probe.

CL = 20 pF

33291L

Under

Test

VDD = 5.0 V

VPull-Up = 2.5 V

RL = 1.0 kΩ

CL represents the total capacitance of the test fixture and probe.

SCLK

(Low-to-High)

(High-to-Low)

tVALID

tDLY(LH)

tDLY(HL)

0.2 VDD

0.7 VDD

tR(SO)

tF(SO)

0.7 VDD

0.2 VDD

0.7 VDD

50%

0.2 VDD

tR(SI)

< 50 ns

tF(SI)

5.0 V

VOH

VOL

VOH

VOL

SO (Low-to-High) is for an output with internal conditions such that

the low-to-high transition of CS causes the SO output to switch from

high to low.

90%

10%

90%

(High-to-Low)

(Low-to-High)

0.2 VDD

0.7 VDD

< 50 ns

tR(SI)

tF(SI)

tSO(EN)

tSO(DIS)

tSO(EN)

tSO(DIS)

VTri-State

5.0 V

tSO(dis

VTri-State

VOH

1. SO (high-to-low) waveform is for SO output with internal conditions such

that SO output is low except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state; e.g., open load.

2. SO (low-to-high) waveform is for SO output with internal conditions such

that SO output is high except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state; e.g., shortened load.

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