33291L datasheet(8/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33291L

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING

Output Rise Time (VPWR = 13 V, RL = 26 Ω)

(26)

0.4

5.0

μs

Output Fall Time (VPWR = 13 V, RL = 26 Ω)

(26)

0.4

5.0

μs

Output Turn-ON Delay Time (VPWR = 13 V, RL = 26 Ω)

(27)

tdly(on)

1.0

μs

Output Turn-OFF Delay Time (VPWR = 13 V, RL = 26 Ω)

(28)

tdly(off)

1.0

μs

Output Short Fault Disable Report Delay (29)

SFPD = 0.2 x VDD

tdly(sf)

150

250

μs

Output OFF Fault Report Delay (30)

SFPD = 0.2 x VDD

tdly(off)

150

250

μs

DIGITAL INTERFACE TIMING

Required Low State Duration for RST (VIL < 0.2 VDD)

(31)

tw(RST)

–

167

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)

tlead

–

167

Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)

tlag

–

167

SI to Falling Edge of SCLK (Required for Setup Time)

tSI(su)

–

Falling Edge of SCLK to SI (Required for Hold Time)

tSI(hold)

–

SO Rise Time (CL = 200 pF)

tr(SO)

–

SO Fall Time (CL = 200 pF)

tf(SO)

–

SI, CS, SCLK, Incoming Signal Rise Time (32)

tr(SI)

–

SI, CS, SCLK, Incoming Signal Fall Time (32)

tf(SI)

–

Time from Falling Edge of CS to SO Low Impedance (33)

tSO(en)

–

110

Time from Rising Edge of CS to SO High Impedance (34)

tSO(dis)

–

110

Time from Rising Edge of SCLK to SO Data Valid (35)

0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF

tvalid

–

105

Notes

26.

Output Rise and Fall time respectively measured across a 26

Ω resistive load at 10% to 90% and 90% to 10% voltage points.

27.

Output Turn-ON Delay time measured from 50% rising edge of CS to 90% of Output OFF voltage (VPWR) with RL = 26 Ω resistive load.

28.

Output Turn-OFF Delay time measured from 50% rising edge of CS to 10% of Output OFF voltage (VPWR) with RL = 26 Ω resistive load.

29.

Propagation time of Short Fault Disable Report measured from 50% rising edge of CS to 10% Output OFF voltage (VPWR), VPWR =

6.0 V and SFPD = 2.0 x VDD.

30.

Output OFF Fault Report Delay measured from 50% rising edge of CS to 10% rising edge of Output OFF voltage (VPWR).

31.

RST

Low duration measured with outputs enabled and going to OFF or disabled condition.

32.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

33.

Time required for output status data to be available for use at the SO pin.

34.

Time required for output status data to be terminated at the SO pin.

35.

Time required to obtain valid data out from SO following the rise of SCLK. See Figure 6, page 9.

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