TUSB6015ZQE

SLLS937

REVISION 1.4 SEPTEMBER 12, 2008

Synchronous Burst Write Access

Note: RDY going low is asynchronous to t_scsn_rdy. Going high, it is synchronous to CLK. Valid Data Time programmable through Device

Wait Count Register. For Wait Count values other than 0 or 1 (when DMAREQ is used), t_wr_acc = Wait Count + 1.

PARAMETER

MIN

MAX

UNIT

t_clk

Cycle Time (max 67.5 MHz)

14.8

ns

t_scsnh_scsnl

Delay time, SCSn high to SCSn low

8

ns

t_acsnh_scsnl

Delay time, ACSn high to SCSn low

8

ns

t_scsn

Delay time, SCSn low to first rising edge of CLK

3ns

1+3ns

CLK

t_scs_off

CLK to SCSn high

1+3ns

Sys Clk

t_wdata_s

Data setup to CLK high

3.75

ns

t_wdata_h

Data hold time

0.6

ns

t_rdy

CLK to RDY output delay

2.2

8.2

ns

t_add_advn_h

Address Hold

0.8

ns

t_scsnl_advn_s

SCSn low Setup to ADVn high

12

ns

t_add_advn_s

Address Setup to ADVn high

12

ns

t_advn

ADVn low pulse

7

ns

t_advn_wen

ADVn high to WEn low

1+3ns

CLK

t_wen_off

CLK to WEn high

1+3ns

Sys Clk

WEn setup to CLK high

3.75

ns

t_wen

WEn hold time

0

t_wr_acc

Valid Data Time (with DMAREQ)

1

1

32

2

CLK

t_scsn_rdy

SCSn low to RDY valid low

7

ns

t_scsn_rdy_z

SCSn high to RDY high-Z

7

ns

1

Device Wait Count Register = 0 or 1.

2

Device Wait Count Register = 31.

16

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