STW8019 datasheet(33/66 Pages) STMICROELECTRONICS

33 / 66 page

Control registers

STw8009/STw8019

32/65

Note:

Bits ‘ph_rst_mode(1:0)’ are automatically set back to ‘00’ following the oscillator reset in

modes ‘01’ and ‘10’.

val_422_mux: should be programmed to “1” only after each reset.

blk_all: blanking of all video lines

(*) 0 = disabled

1 = enabled

(all inputs are ignored - 80hex instead of Cr and Cb and 10hex instead of Y and Y4)

(*) = DEFAULT mode when not_reset pin is active (LOW level)

hok: Hamming decoding of frame sync flag embedded within ITU-R656 / D1 compliant

YCrCb streams

0 = Consecutive errors

(*) 1 = A single or no error

Note:

Signal quality detector is issued from Hamming decoding of EAV, SAV from YcrCb

atfr: Frame synchronization flag

(*) 0 = encoder not synchronized

1 = in slave mode: encoder synchronized

configuration8

Address: 0x0008

Type: R/W

content

ph_rst_

mode1

ph_rst_

mode0

xxx

val_422_

mux

blk_all

xxx

default

1000

Table 12.

ph_rst_mode[1:0]:sub-carrier phase reset

ph_rst_mode

update mode

(*)

disabled

enabled - phase is updated with value from phase buffer

video line. In the mean time, the increment is updated with

hard or soft values depending on selreg_inc value (see

enabled - phase is updated with values from Registers 10 and

11, based on the next increment update from cfc (depending

on cfc loading moment and Register6 cfc(1:0) bits.

enabled - phase is reset following the detection of rst bit on cfc

line, up to 9 pix_clk after loading of cfc’s LSB.

Address: 0x0009

Type: Read only

content

hok

atfr

fieldct2

fieldct1

fieldct0

jump

STW8019 датащи(PDF) 33 Page - STMicroelectronics

STW8019 датащи(HTML) 33 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

датащи скачать

ссылки URL