STW8019 datasheet(26/66 Pages) STMICROELECTRONICS

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STw8009/STw8019

Control registers

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5.2

Description

(*) = DEFAULT mode when not_reset pin is active (LOW level)

Caution:

All binary values quoted should be understood as MSB........LSB

5.2.1

DENC registers

polh: synchro: active edge of HSYNC selection (when input) or polarity of HSYNC (when

output)

(*) 0 = HSYNC is a negative pulse (128 Tpix_clk wide) or falling edge is active

1 = HSYNC is a positive pulse (128 Tpix_clk wide) or rising edge is active

polv: synchro: active edge of ODDEV/VSYNC selection (when input)

0 = falling edge of ODDEV flags start of field1 (odd field) or VSYNC is active low

(*) 1 = rising edge of ODDEV flags start of field1 (odd field) or VSYNC is active high

configuration0

Address: 0x0000

Type: R/W

content

std1

std0

sync2

sync1

sync0

polh

polv

freerun

default

0100

Table 4.

std1, std0

std1

std0

Standard selected

PAL BDGHI

PAL N (see bit set-up)

(*)

NTSC M(1)

Standard on hardware reset is NTSC; any standard modification selects automatically the right

parameters for correct subcarrier generation.

PAL M

Table 5.

sync2, sync1, sync0

sync2

sync1

sync0

Configuration

ODDEV-only based SLAVE mode (frame locked)

‘F’ based SLAVE mode (frame locked)

(*)

ODDEV+HSYNC based SLAVE mode (line locked)

VSYNC-only based SLAVE mode (frame locked)(1)

In VSYNC-only based slave mode (sync[2:0]=”100”), HSYNC is nevertheless needed as an input.

VSYNC+HSYNC based SLAVE mode (line locked)

MASTER mode

AUTOTEST mode (colour bar pattern)

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