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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA333BWQS13TR датащи(PDF) 38 Page - STMicroelectronics |
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STA333BWQS13TR датащи(HTML) 38 Page - STMicroelectronics |
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38 / 71 page  Register description STA333BWQS 38/71 For each configuration the PWM from the digital driver are mapped in different way to the power stage: 2.0 channels, two full bridges (OCFG = 00) " DDX1A ' OUT1A " DDX1B ' OUT1B " DDX2A ' OUT2A " DDX2B ' OUT2B " DDX3A ' OUT3A " DDX3B ' OUT3B " DDX4A ' OUT4A " DDX4B ' OUT4B " DDX1A/1B configured as ternary " DDX2A/2B configured as ternary " DDX3A/3B configured as lineout ternary " DDX4A/4B configured as lineout ternary On channel 3 line out (LOC bits = "00") the same datas as channel 1 processing are sent. On channel 4 line out (LOC bits = "00") the same datas as channel 2 processing are sent. In this configuration, no volume control or EQ have effect on channel 3 and 4. In this configuration the PWM slot phase is the following as shown in the next figures: Figure 14. 2.0 channels (OCFG = 00) PWM slots. OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B |
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