STA309A datasheet(22/67 Pages) STMICROELECTRONICS

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Registers

STA309A

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7.2

7.2.1

Configuration register A (0x00)

The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore, the internal clocks are:

65.536 MHz for 32 kHz

90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD

98.304 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs). The relationship between the input clock and the input sample rate is

determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits

determine the PLL factor generating the internal clock and the IRn bits determine the

oversampling ratio used internally.

0x51

PSC1

RCV11

RCV10

RCV9

RCV8

RCV7

RCV6

RCV5

RCV4

0x52

PSC2

RCV3

RCV2

RCV1

RCV0

CNV11

CNV10

CNV9

CNV8

0x53

PSC3

CNV7

CNV6

CNV5

CNV4

CNV3

CNV2

CNV1

CNV0

Table 8.

Addr

Name

321

COS1

COS0

DSPB

IR1

IR0

MCS2

MCS1

MCS0

001

Table 9.

MSC bits

Bit

RST

Name

Description

0RW

MCS0

Master clock select: selects the ratio between the input

I2S sample frequency and the input clock.

1RW

MCS1

2RW

MCS2

Table 10.

MSC sample rates

Input sample rate

fs (kHz)

MCS[2:0]

1XX

011

010

001

000

32, 44.1, 48

128 * fs

256 * fs

384 * fs

512 * fs

768 * fs

88.2, 96

64 * fs

128 * fs

192 * fs

256 * fs

384 * fs

176.4, 192

64 * fs

128 * fs

192 * fs

256 * fs

384 * fs

DSD

2 * fs

4 * fs

6 * fs

8 * fs

12 * fs

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