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ORSPI4 датащи(PDF) 263 Page - Lattice Semiconductor |
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ORSPI4 датащи(HTML) 263 Page - Lattice Semiconductor |
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263 / 263 page ![]() Lattice Semiconductor ORCA ORSPI4 Data Sheet 263 October 2004 03.0 Datasheet is now Final Status for production release of the device. Clock Rates under High Performance Memory Controller for Interface to External Buffer Memory has been updated to 175MHz DDR performance has been updated to 175MHz in the introduction section. FPGA Logic Overview section has been updated. Recommended Operating Conditions has been updated. ORSPI4 Post-Configuration Stabdby CurrentTable has been updated. ORSPI4 Combined SPIA and SPIB Worst Case Power Table has been updated. ORSPI4 QDR Memory Controller Worst Case Power Table has been updated. ORSPI4 SERDES Worst Case Power Table has been updated with footnote 2. Supported Data Rates Table has been updated. System Timing Reference Points has been updated. SPI4.2 Timing Points with Respect to Clock Edge has been added. SPI4.2 Data Interface Table has been updated. SPI4.2 Receive Timing Points with Respect to Clock Edge has been added." SPI4.2 Receive Data Interface Timing has been updated. Data Path Interface Timing for Static Alignment has been updated. Data Path Parameters for Dynamic Alignment has been updated. Status Channel Reference Points with Respect to Clock Edge (LVDS and LVTTL I/Os) has been updated. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode February 2005 04.0 Status Channel Reference Points with Respect to Clock Edge (Edge Aligned Legacy Mode) has been updated. Status Path Interface ORSPI4 Timing in Legacy Mode has been updated. Channel Output Jiffer (3.125 Gbits/s) has been updated. Channel Output Jitter (2.5 Gbits/s) has been updated. HSTL Class I and II section has been updated. HSTL Class II DC Operating Specifications has been updated. Supported Data Rtes (36-Bit QDR-II, 32 bit Considered Data) Table has been updated. Memory Controller Output Timing Specifications has been updated. Memory Controller Input Timing Specifications have been updated. Memory Controller Input Timing Specifications have been updated. Recommended Power Supply Connections section has been updated. Recommended Power Supply Filtering Scheme section has been updated. Commercial Ordering Information Table and Industrial Ordering Information Table have been updated for production release of the ORSPI4. April 2005 05.0 Released 1156-fpBGA Pb-free devices. October 2007 06.0 Added 1036-ball ftSBGA information per PCN#16A-07 (package conversion from 1036- fpSBGA to 1036-ftSBGA). Date Version Change Summary |
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