ORSPI4 datasheet(174/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

174

ORSPI4 Power Tables

Table 50. ORSPI4 Post-conﬁguration Standby Current

* Conditions: TA = 85°C, VDD15 = 1.575V, VDD33 = 3.6V, VDDIO = 3.6V, internal oscillator running, no output loads, inputs VDDIO or VSS.

Standby current is tested with the embedded core in a powered down state.

Table 51. ORSPI4 Combined SPIA and SPIB Worst Case Power Table

* Power measured with both SPIA and SPIB operating simultaneously. AC power only. Power numbers do not include post-conﬁguration

standby current (see Table 50). FPGA power not included. FPGA power is application dependent – See the ORCA Series 4 Data Sheet to

calculate FPGA power.

Conditions: TA = 85°C, VDD15 = 1.575V, VDD33 = 3.6V, VDDIO = 3.6V.

Table 52. ORSPI4 QDR Memory Controller Worst Case Power Table

Note: In many applications the PLL can be disabled to reduce power.

Temperature: -40

°C to 125°C, Power Supplies: VDD15, VDDH = 1.575V, VDD33 = 3.6V, Data Pattern: PRBS 2^31-1

Parameter

Clock Frequency

Unit

VDD15*

VDD33*

VDDH

Post-conﬁguration

Standby Current

500

300

200

Parameter

Reference

Clock

Frequency

VDD15

VDDA_SPI[A:D]

Power*

VDD33

Power*

Power per SPI

Interface*

Unit

450 MHz (900 Mbps) with Dynamic Alignment

Frequency

112.5 MHz

Total

0.887

0.518

1.405

325 MHz (650 Mbps) with Static Alignment

Frequency

81.25 MHz

Total

0.570

0.486

1.056

311 MHz (622 Mbps) with Static Alignment

Frequency

77.75 MHz

Total

0.513

0.493

1.006

100 MHz (200 Mbps) Quarter Rate

Frequency

200 MHz

Total

0.082

0.436

0.518

78 MHz (156 Mbps) Quarter Rate

Frequency

156 MHz

Total

0.017

0.407

0.424

Parameter

Value

Unit

Clock Frequency

160

MHz

VDD15, VDDH Power

226.8

VDD33 Power

46.8

Total Power

273.6

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