ORSPI4 datasheet(103/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

103

SERDES Functional Description

The SERDES portion of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and Serial-

ize/Deserialize (SERDES) blocks and supports 8b/10b (IEEE 802.3.2002) encoded serial links. It is intended for

high-speed serial backplane data transmission. Figure 47 shows the SERDES top level block diagram and the

basic data ﬂow to and from the SERDES. Boundary scan for the SERDES only includes programmable I/Os and

does not include any of the embedded block I/Os.

Figure 47. SERDES Top Level Block Diagram.

The SERDES serial channels can each operate at up to 3.7 Gbits/s (2.96 Gbits/s data rate) with a full-duplex syn-

chronous interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for

the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical link

monitoring. Overviews of the various blocks in the SERDES are presented in the following paragraphs

ORSPI4 SERDES Functional Block Overview

The SERDES portion of the core contains one transceiver block for serial data transmission at a selectable data

rate of 0.6-3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core

blocks and high-speed CML interfaces to the serial links.

The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high-

speed (up to 3.7 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each

channel to retime the data, then de-multiplexes the data down to parallel bytes and an accompanying clock.

The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbits/s serial data for off-

chip communication. The transmitter generates the necessary high-speed clocks for operation from a lower speed

reference clock.

The transceivers are controlled and conﬁgured through the system bus in the FPGA logic and through the external

8-bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable

and write-able. There are also global registers for control of common circuitry and functions.

The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can sup-

port either Ethernet or Fibre Channel speciﬁcations for serial encoding/decoding, special characters, and error

detection.

The user can disable the 8b/10b decoder to receive raw 10-bit words which will be rate reduced by the SERDES. If

this mode is chosen, the user must bypass the multi-channel alignment FIFOs.

SERDES w/

CLOCK/DATA

BYTE-

WIDE

DATA

8b/10b

DECODER/ENCODER

4 FULL-

0.6 Gbits/s

DATA

DUPLEX

SERIAL

CHANNELS

3.7 Gbits/s

0.6 Gbits/s

DATA

3.7 Gbits/s

CML

I/Os

ORCA

SERIES 4

FPGA LOGIC

STANDARD

FPGA I/Os

4:1 MUX/1:4 DEMUX

RECOVERY

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