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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM6685TR датащи(PDF) 40 Page - STMicroelectronics |
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PM6685TR датащи(HTML) 40 Page - STMicroelectronics |
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40 / 52 page  Monitoring and protections PM6685 40/52 Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple. If the ripple is very small (lower than approximately 30mV), a further compensation network, named virtual ESR network, is needed. This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network. The complete control schematic is represented in Figure 37. Figure 37. Virtual ESR network The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent ESR RESR. A good trade-off is to design the network in order to achieve an RESR given by: Equation 26 where ∆IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage. It should be chosen higher than approximately 30mV. The stability of the system depends firstly on the output capacitor value and on RTOT: + - V Vrr C CO OM MP P g gm m O OU UT T R RF Fb b1 1 R RF Fb b2 2 V Vrr + P PW WM M C Co om mp pa arra atto orr C CIINNTT R RIINNTT C CFFIILLTT t Vr C COOUUTT COMP PIN VOLTAGE L L D D OUTPUT VOLTAGE I=gm(V1-Vr) V V1 1 C C R R1 1 R R t t T T NODE VOLTAGE ∆V ∆V1 R ROOUUTT ∆V1 out L RIPPLE ESR R I V R − ∆ = |
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