PM6670ASTR datasheet(31/54 Pages) STMICROELECTRONICS

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PM6670AS

Device description

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VDDQ output voltage can be set in the range from 0.9 V to 2.6 V. Adjustable mode

automatically switches DDRSEL pin to become the power saving algorithm selector: if tied

to +5 V, the forced-PWM (fixed frequency) control is performed. If grounded or connected to

VREF pin (1.237 V reference voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are

respectively selected.

7.1.5

Current sensing and current limit

The PM6670AS switching controller uses a valley current sensing algorithm to properly

handle the current limit protection and the inductor current zero-crossing information. The

current is sensed during the conduction time of the low-side MOSFET. The current sensing

element is the on-resistance of the low-side switch. The sensing scheme is visible in

Figure 34

Figure 34. Current sensing scheme

An internal 100

µA current source is connected to C

SNS pin that is also the non-inverting

input of the positive current limit comparator. When the voltage drop developed across the

sensing parameter equals the voltage drop across the programming resistor RILIM, the

controller skips subsequent cycles until the overcurrent condition is detected or the output

UV protection latches off the device (see Section 7.1.11: Over voltage and under voltage

protections on page 36

Table 1. Mode-Of-Operation settings summary

Mode

DDRSEL

VDDQ

Operating mode

VMODE > 4.3 V

VDDRSEL > 4.2 V

1.8 V

Pulse-Skip

1 V < VDDRSEL < 3.5 V

1.5 V

<0.5 V

VMODE < 3.7 V

VDDRSEL > 4.2 V

ADJ

Forced-PWM

1V < VDDRSEL < 3.5 V

Non-Audible Pulse-skip

VDDRSEL < 0.5 V

Pulse-Skip

HGATE

PHASE

CSNS

LGATE

PGND

PM6670

100µA·

ILIM

OUT

VALLEY·RDSon

HGATE

PHASE

CSNS

LGATE

PGND

PM6670

100µA·

ILIM

OUT

VALLEY·RDSon

PM6670AS

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