TDA7540N datasheet(35/76 Pages) STMICROELECTRONICS

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TDA7540N

Functional description

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Frequency generation for phase comparison

The RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5-

bit A-divider. The 5-bit register (PC0 to PC4) controls this divider. In parallel the output of the

prescaler connects to an 11-bit B-divider. The 11-bit PC register (PC5 to PC15) controls this

divider

Dividing range behind VCO divider:

fVCOdiv = [33 x A + (B + 1 - A) x 32] x fREF

fVCOdiv = (32 x B + A + 32) x fREF

Important: For correct operation: A ≤ 32; B ≥ A

Three state phase comparator

The phase comparator generates a phase error signal according to phase difference

between fSYN and fREF. This phase error signal drives the charge pump current generator.

Charge pump current generator

This system generators signed pulses of current. The phase error signal decides the

duration and polarity of those pulses. The current absolute values are programmable by A

Inlock detector

Switching the chargepump in low current mode can be done either via software or

automatically by the inlock detector, by setting bit LDENA to "1".

After reaching a phase difference about lower than 40nsec the chargepump is forced in low

current mode. A new PLL divider alternation by I2C-Bus will switch the chargepump in the

high current mode.

Low noise CMOS op-amp

An internal voltage divider at pin VREF2 connects the positive input of the low noise op-

amp. The charge pump output connects the negative input. This internal amplifier in

cooperation with external components can provide an active filter. The negative input is

switchable to three input pins, to increase the flexibility in application. This feature allows two

separate active filters for different applications.

While the high current mode is activated LPHC output is switched on.

4.4.2

IF counter block

The aim of IF counter is to measure the intermediate frequency of the tuner for AM and FM

mode. The input signal for FM and AM upconversion is the same 10.7MHz IF level after

limiter. AM 450KHz signal is coming from narrow filtered IF2 before demodulation. A switch

controlled by IF counter mode (IFCM) is choosing the input signal for IF counter.

The grade of integration is adjustable by eight different measuring cycle times. The

tolerance of the accepted count value is adjustable, to reach an optimum compromise for

search speed and precision of the evaluation.

The IF-counter mode

The IF counter works in 3 modes controlled by IFCM register.

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