M48T129Y datasheet(18/30 Pages) STMICROELECTRONICS

18 / 30 page

M48T129Y, M48T129V

18/30

Figure 13. Back-up Mode Alarm Waveforms

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address

1FFF7h. Bits BMB4-BMB0 store a binary multiplier

and the two lower order bits RB1-RB0 select the

resolution, where 00 = 1/16 second, 01 = 1/4 sec-

ond, 10 = 1 second, and 11 = 4 seconds. The

amount of time-out is then determined to be the

multiplication of the five-bit multiplier value with the

resolution. (For example: writing 00001110 in the

Watchdog Register = 3*1 or 3 seconds).

Note: Accuracy of timer is a function of the select-

ed resolution.

If the processor does not reset the timer within the

specified period, the M48T129Y/V sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset. WDF is reset by

reading the Flags Register (Address 1FFF0h). The

most significant bit of the Watchdog Register is the

Watchdog Steering Bit (WDS). When set to a '0,'

the watchdog will activate the IRQ/FT pin when

timed-out. When WDS is set to a '1,' the watchdog

will output a negative pulse on the RST pin for 40

to 200 ms. The Watchdog register and the FT Bit

will reset to a '0' at the end of a Watchdog time-out

when the WDS Bit is set to a '1.'

The watchdog timer can be reset by two methods:

a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI); or

the microprocessor can perform a WRITE of

the Watchdog Register.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin. In the order to perform a software reset

of the watchdog timer, the original time-out period

can be written into the Watchdog Register, effec-

tively restarting the count-down cycle.

Should the watchdog timer time-out, and the WDS

Bit is programmed to output an interrupt, a value of

“00h” needs to be written to the Watchdog Regis-

ter in order to clear the IRQ/FT pin. This will also

disable the watchdog function until it is again pro-

grammed correctly. A READ of the Flags Register

will reset the Watchdog Flag (Bit D7; Register

1FFF0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog function is set to output to

the IRQ/FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

AI01678C

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

tREC

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