M48T129Y datasheet(7/30 Pages) STMICROELECTRONICS

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M48T129Y, M48T129V

OPERATING MODES

Figure 4., page 5 illustrates the static memory ar-

ray and the quartz controlled clock oscillator. The

clock locations contain the century, year, month,

date, day, hour, minute, and second in 24 hour

BCD format. Corrections for 28, 29 (leap year -

valid until 2100), 30, and 31 day months are made

automatically. The nine clock bytes (1FFFFh-

1FFF9h and 1FFF1h) are not the actual clock

counters, they are memory locations consisting of

BiPORT™ READ/WRITE memory cells within the

static RAM array.

The M48T129Y/V includes a clock control circuit

which updates the clock bytes with current infor-

mation once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array. Byte

1FFF8h is the clock control register. This byte con-

trols user access to the clock information and also

stores the clock calibration setting.

Byte 1FFF7h contains the watchdog timer setting.

The watchdog timer can generate either a reset or

an interrupt, depending on the state of the Watch-

dog Steering Bit (WDS). Bytes 1FFF6h-1FFF2h

include bits that, when programmed, provide for

clock alarm functionality. Alarms are activated

when the register content matches the month,

date, hours, minutes, and seconds of the clock

registers. Byte 1FFF1h contains century informa-

tion. Byte 1FFF0h contains additional flag informa-

tion pertaining to the watchdog timer, the alarm

condition and the battery status. The M48T129Y/V

also has its own Power-Fail Detect circuit. This

control circuitry constantly monitors the supply

voltage for an out of tolerance condition. When

VCC is out of tolerance, the circuit write protects

the TIMEKEEPER® register data and external

SRAM, providing data security in the midst of un-

predictable system operation. As VCC falls below

Battery Back-up Switchover Voltage (VSO), the

control circuitry automatically switches to the bat-

tery, maintaining data and clock operation until

valid power is restored.

Table 2. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

1. See Table 12., page 23 for details.

Mode

VCC

DQ0-DQ7

Power

Deselect

4.5 to 5.5V

3.0 to 3.6V

VIH

High Z

Standby

WRITE

VIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)

High Z

CMOS Standby

Deselect

≤ VSO(1)

High Z

Battery Back-up Mode

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