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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STTS424E02BDA3F датащи(PDF) 30 Page - STMicroelectronics |
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STTS424E02BDA3F датащи(HTML) 30 Page - STMicroelectronics |
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30 / 51 page  SPD EEPROM operation STTS424E02 30/51 Figure 10. Result of setting the write protection 5.4 Setting the write protection The Write Control (WC) is tied Low, hence the write protection of the memory array is dependent on whether software write-protection has been set. Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh) to be write protected irrespective of subsequent states of the Write Control (WC) signal. Software write-protection is handled by three instructions: ● SWP: Set write protection ● CWP: Clear write protection ● PSWP: Permanently set write protection The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. Table 21. Operating modes Mode RW bit WC(1) 1. X = VIH or VIL. Bytes Initial sequence Current address read 1 X 1 START, device select, RW = 1 Random address read 0X 1 START, device select, RW = 0, address 1 X reSTART, device select, RW = 1 Sequential read 1 X ≥ 1 Similar to current or random address read Byte write 0 V IL 1 START, device select, RW = 0 Page write 0 V IL ≤ 16 START, device select, RW = 0 Default EEPROM memory area state before write access to the Protect Register AI01936C Standard Array FFh Standard Array 80h 7Fh 00h Standard Array FFh Write Protected Array 80h 7Fh 00h State of the EEPROM memory area after write access to the Protect Register Memory Area |
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