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M41T93RMY6F датащи(PDF) 24 Page - STMicroelectronics |
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M41T93RMY6F датащи(HTML) 24 Page - STMicroelectronics |
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24 / 51 page ![]() Clock operation M41T93 24/51 The on-chip capacitance can be calculated as follows: For example: CLOAD (12h = x0000000) = 12.5 pF CLOAD (12h =11001000) = 3.5 pF and CLOAD (12h = 00100111) = 17.4 pF The oscillator sees a minimum of 3.5 pF with no programmable load capacitance selected. Note: These are typical values, and the total load capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the analog calibration register value. Any invalid value of analog calibration will result in the default capacitance of 25 pF. The combination of analog and digital trimming can give up to –93 to +156 ppm of the total adjustment. Figure 11 on page 25 represents a typical curve of clock ppm adjustment versus the Analog Calibration value. This curve may vary with different crystals, so it is good practice to evaluate the crystal to be used with an M41T93 device before establishing the adjustment values for the application in question. C LOAD AC6 AC0 value – decimal , () 0.25pF × [] 7pF + = |
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