M41ST85WMH6 datasheet(15/41 Pages) STMICROELECTRONICS

номер детали	M41ST85WMH6

подробное описание детали	3.0/3.3V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor

PDF	41 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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M41ST85W

Operating modes

15/41

2.2

Read mode

In this mode the master reads the M41ST85W slave after setting the slave address (see

Figure 9). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the

word address 'An' is written to the on-chip address pointer. Next the START condition and

slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point

the master transmitter becomes the master receiver.

The data byte which was addressed will be transmitted and the master receiver will send an

Acknowledge Bit to the slave transmitter (see Figure 10 on page 16). The address pointer is

only incremented on reception of an Acknowledge Clock. The M41ST85W slave transmitter

will now place the data byte at address An+1 on the bus, the master receiver reads and

acknowledges the new byte and the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a Stop Condition or when

the pointer increments to a non-clock or RAM address.

Note:

This is true both in READ Mode and WRITE Mode.

An alternate READ Mode may also be implemented whereby the master reads the

M41ST85W slave without first writing to the (volatile) address pointer. The first address that

is read is the last one stored in the pointer (see Figure 11 on page 16).

Figure 9.

Slave address location

AI00602

R/W

SLAVE ADDRESS

START

100

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