XC2000 datasheet(43/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-15

V1.0, 2007-06

ArchitectureX2K, V1.0

2.3

On-Chip Peripheral Blocks

The XC2000 Family clearly separates peripherals from the core. This structure permits

the maximum number of operations to be performed in parallel and allows peripherals to

be added or deleted from family members without modifications to the core. Each

functional block processes data independently and communicates information over

common buses. Peripherals are controlled by data written to the respective Special

Function Registers (SFRs). These SFRs are located within either the standard SFR area

(00’FE00H … 00’FFFFH), the extended ESFR area (00’F000H … 00’F1FFH), or within

the internal IO area (00’E000H … 00’EFFFH).

These built-in peripherals either allow the CPU to interface with the external world or

provide functions on-chip that otherwise would need to be added externally in the

respective system.

The XC2000 generic peripherals are:

• Two General Purpose Timer Blocks (GPT1 and GPT2)

• A Watchdog Timer

• A Capture/Compare unit (CAPCOM2)

• Up to Four Enhanced Capture/Compare units (CCU60, CCU61, CCU62, CCU63)

• Two 10-bit Analog/Digital Converters (ADC0, ADC1)

• A Real Time Clock (RTC)

• Thirteen I/O ports with a total of 118(75) I/O lines

Because the LXBus is the internal representation of the external bus, it does not support

bit-addressing. Accesses are executed by the EBC as if it were external accesses. The

LXBus connects on-chip peripherals to the CPU:

• MultiCAN module with up to 5 CAN nodes and gateway functionality

• Three Serial Interface Modules providing six serial channels

Each peripheral also contains a set of Special Function Registers (SFRs) which control

the functionality of the peripheral and temporarily store intermediate data results. Each

peripheral has an associated set of status flags. Individually selected clock signals are

generated for each peripheral from binary multiples of the master clock.

Note: For an overview of the available peripherals for the different derivatives, please

refer to Table 1-1 "XC2000 Derivative Synopsis" on Page 1-2.

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