C167CS-4RM datasheet(77/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-27

V2.0, 2000-07

Figure 4-8

Implicit CP Use by Short GPR Addressing Modes

The Stack Pointer SP

This non-bit addressable register is used to point to the top of the internal system stack

(TOS). The SP register is pre-decremented whenever data is to be pushed onto the

stack, and it is post-incremented whenever data is to be popped from the stack. Thus,

the system stack grows from higher toward lower memory locations.

Since the least significant bit of register SP is tied to ‘0’ and bits 15 through 12 are tied

to ‘1’ by hardware, the SP register can only contain values from F000H to FFFEH. This

allows to access a physical stack within the internal RAM of the C167CS. A virtual stack

(usually bigger) can be realized via software. This mechanism is supported by registers

STKOV and STKUN (see respective descriptions below).

The SP register can be updated via any instruction, which is capable of modifying an SFR.

Note: Due to the internal instruction pipeline, a POP or RETURN instruction must not

immediately follow an instruction updating the SP register.

Stack Pointer Register

SFR (FE12H/09H)

Reset Value: FC00H

98765

43210

1111

rwh

Bit

Function

Modifiable portion of register SP

Specifies the top of the internal system stack.

For word GPR

accesses

For byte GPR

Control

1111

Specified by reg or bitoff

Context

Pointer

4-Bit GPR

Address

MCD02005

Internal

GPRs

RAM

Must be

within the

RAM area

internal

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