AT91SAM7A2-AI datasheet(32/369 Pages) ATMEL

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PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

Early Read Protocol

Early read protocol provides more memory access time for a read access by asserting

NRD at the beginning of the read cycle. This mode is selected by setting the DRP bit in

the AMC_MCR register.

In the case of successive read cycles in the same memory, NRD remains active contin-

uously. Since a read cycle normally limits the speed of operation of the external memory

system, early read protocol can allow a faster timing of the EBI to be used. However, an

extra data float wait state is required in some cases to avoid contentions on the external

bus, this is explained in “Data Float Wait State” on page 34.

Figure 17. Early Read Address

Write Access

In a write access cycle, NWE (or NWR0, NWR1) is active during the second half of the

write cycle.

The first half of the write cycle allows time to ensure completion of the previous access

as well as the address and NCS set up time before NEW (or NWR0, NWR1) is asserted.

During a write external memory access, NCS is set low and ADDR is valid at the begin-

ning of the access while NWE (or NWR0, NWR1) goes low only in the second half of the

write cycle to avoid bus conflict.

Figure 18. Write Access

NWE (or NWR0, NWR1) goes high at the end of the write cycle, this is not true if a wait

state is asserted.

Wait State

Each chip select line can be programmed to insert one or more wait states during an

external access. This is done by setting the WSE bit in the corresponding AMC_CSRx

The correspondence between the number of standard wait states programmed and the

number of cycles during which the NWE pulse is held low is as follows:

Address Valid

Address

NCS

NOE/NRD

Address Valid

Address

NCS

NWE

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