AT91SAM7A2-AI datasheet(97/369 Pages) ATMEL

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PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

SPSR, masking or unmasking the interrupts depending on the state saved in the

SPSR (the previous state of the ARM core).

Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was

just about to mask IRQ interrupts when the mask instruction was interrupted. Hence,

when the SPSR is restored, the mask instruction is completed (IRQ is masked).

Fast Interrupt Sequence

For details on the registers mentioned in the steps below, refer to the ARM7TDMI

Embedded Core Datasheet.

It is assumed that:

•

The Generic Interrupt Controller has been programmed, GIC_SVR[0] is loaded with

a fast interrupt service routine address and the fast interrupt is enabled.

•

The Instruction at address 0x1C (FIQ exception vector address) is:

ldr pc, [pc, #-&F20]

•

Nested Fast Interrupts are not needed by the user.

When nFIQ is asserted, if the F bit of CPSR is 0, the sequence is:

CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded

in the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded with

0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts

r14_fiq, incrementing it by 4.

The ARM core enters FIQ mode.

When the instruction loaded at address 0x1C is executed, the Program Counter

is loaded with the value read in GIC_FVR. Reading the GIC_FVR automatically

clears the fast interrupt (source 0 connected to the FIQ line), if it has been pro-

grammed to be edge triggered. In this case only, it de-asserts the nFIQ line on

the processor.

The previous step branches to the corresponding interrupt service routine. It is

not necessary to save the Link Register (r14_fiq) and the SPSR (SPSR_fiq) if

nested fast interrupts are not needed.

The Interrupt Handler can then proceed as required. It is not necessary to save

registers r8 to r13 because FIQ mode has its own dedicated registers and the

user registers r8 to r13 are banked. The other registers, r0 to r7, must be saved

before being used, and restored at the end (before the next step). Note that if the

fast interrupt is programmed to be level sensitive, the source of the interrupt must

be cleared during this phase in order to de-assert the nFIQ line.

Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by

4 (with instruction sub pc, lr, #4 for example). This has the effect of return-

ing from the interrupt to whatever was being executed before, and of loading

CPSR with the SPSR, masking or unmasking the fast interrupt depending on the

state saved in the SPSR.

Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was

just about to mask FIQ interrupts when the mask instruction was interrupted. Hence

when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).

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