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DP80390 датащи(PDF) 10 Page - Digital Core Design |
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DP80390 датащи(HTML) 10 Page - Digital Core Design |
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10 / 84 page ![]() DP80390 Instructions set details - 10 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 2.2.4. DATA TRANSFERS Mnemonic Description Code Bytes Cycles MOV A,Rn Move register to accumulator 0xE8-0xEF 1 1 MOV A,direct Move direct byte to accumulator 0xE5 2 2 MOV A,@Ri Move indirect RAM to accumulator 0xE6-0xE7 1 2 MOV A,#data Move immediate data to accumulator 0x74 2 2 MOV Rn,A Move accumulator to register 0xF8-0xFF 1 1 MOV Rn,direct Move direct byte to register 0xA8-0xAF 2 3 MOV Rn,#data Move immediate data to register 0x78-0x7F 2 2 MOV direct,A Move accumulator to direct byte 0xF5 2 2 MOV direct,Rn Move register to direct byte 0x88-8F 2 2 MOV direct1,direct2 Move direct byte to direct byte 85 3 3 MOV direct,@Ri Move indirect RAM to direct byte 86-87 2 3 MOV direct,#data Move immediate data to direct byte 75 3 3 MOV @Ri,A Move accumulator to indirect RAM F6-F7 1 2 MOV @Ri,direct Move direct byte to indirect RAM A6-A7 2 3 MOV @Ri,#data Move immediate data to indirect RAM 76-77 2 2 MOV DPTR,#data16 Load 16-bit constant into active DPH and DPL in LARGE mode 90 3 3 MOV DPTR,#data24 Load 24-bit constant into active DPX, DPH and DPL in FLAT mode 90 4 4 MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator 93 1 5 MOVC A,@A+PC Move code byte relative to PC to accumulator 83 1 4 MOVX A,@Ri Move external RAM (8-bit address) to A E2-E3 1 3* MOVX A,@DPTR Move external RAM (16-bit address) to A E0 1 2* CODE inside ROM/RAM destination XRAM data 4* MOVX @Ri,A Move A to external RAM (8-bit address) all other cases F2-F3 1 5* CODE inside ROM/RAM destination XRAM data 3* MOVX @DPTR,A Move A to external RAM (16-bit address) all other cases F0 1 4* LARGE 3 PUSH direct Push direct byte onto stack FLAT C0 2 3 LARGE 2 POP direct Pop direct byte from stack FLAT D0 2 2 XCH A,Rn Exchange register with accumulator C8-CF 1 2 XCH A,direct Exchange direct byte with accumulator C5 2 3 XCH A,@Ri Exchange indirect RAM with accumulator C6-C7 1 3 XCHD A,@Ri Exchange low-order nibble indirect RAM with A D6-D7 1 3 Table 6. Data transfer * MOVX cycles depends on external data memory access time (READY pin) |
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