CC2430DB datasheet(73/212 Pages) TAOS

73 / 212 page

CC2430

Peripherals : Flash Controller

CC2430 Data Sheet (rev. 2.1) SWRS036F

Page 73 of 211

13.3.2.1

DMA Flash Write

When using DMA write operations, the data to

be written into flash is stored in the XDATA

memory space (RAM or FLASH). A DMA

channel is configured to read the data to be

written from memory, source address, and

write this data to the Flash Write Data register,

FWDATA

, fixed destination address, with the

DMA

trigger

event

FLASH

(TRIG[4:0]=10010 in DMA configuration)

enabled. Thus the Flash Controller will trigger

a DMA transfer when the Flash Write Data

data. The DMA channel should be configured

to perform single mode, byte size transfers

with source address set to start of data block

and destination address to fixed FWDATA (note

that the block size, LEN in configuration data,

must be 4 bytes aligned). High priority should

also be ensured for the DMA channel so it is

not interrupted in the write process. If

interrupted for more than 40 µs the write will

not take place as write bit, FCTL.WRITE, will

be reset.

When the DMA channel is armed, starting a

flash write by setting FCTL.WRITE to 1 will

trigger the first DMA transfer (DMA and Flash

controller handles the reset of the transfer).

Figure 15 shows an example of how a DMA

channel is configured and how a DMA transfer

is initiated to write a block of data from a

location in XDATA to flash memory, assuming

the code is executed from RAM (unified

CODE).

DMA Flash Write from XDATA memory

When performing DMA flash write while

executing code from within flash memory, the

instruction that triggers the first DMA trigger

event FLASH (TRIG[4:0]=10010 DMA in

configuration) must be aligned on a 4-byte

boundary. Figure 14 shows an example of

code that correctly aligns the instruction for

triggering DMA (Note that this code is IAR

specific).

; Write flash and generate Flash DMA trigger

; Code is executed from flash memory

;

#include “ioCC2430.h”

MODULE flashDmaTrigger.s51

RSEG RCODE (2)

PUBLIC halFlashDmaTrigger

FUNCTION halFlashDmaTrigger, 0203H

halFlashDmaTrigger:

ORL FCTL, #0x02;

RET;

END;

Figure 14: Flash write using DMA from flash

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