CC2430DB datasheet(70/212 Pages) TAOS

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CC2430

Peripherals : Power Management and clocks

CC2430 Data Sheet (rev. 2.1) SWRS036F

Page 70 of 211

therefore the calibration may be disabled by

setting register bit SLEEP.OSC32K_CALDIS

to 1. Note that any ongoing calibration will be

completed

when

written

SLEEP.OSC32K_CALDIS.

13.1.4.4

Oscillator and Clock Registers

This section describes the Oscillator and Clock

registers. All register bits retain their previous

values when entering PM2 or PM3 unless

otherwise stated.

CLKCON (0xC6) – Clock Control

Bit

Name

Reset

R/W

Description

OSC32K

R/W

32 kHz clock oscillator select. The 16 MHz high frequency RC

oscillator must be selected as system clock source when this bit is

to be changed.

0 – 32.768 kHz crystal oscillator

1 – 32 kHz RC oscillator

Note: this bit is not retained in PM2 and PM3. After re-entry to PM0

from PM2 or PM3 this bit will be at the reset value 1.

OSC

R/W

System clock oscillator select:

0 – 32 MHz crystal oscillator

1 – 16 MHz high frequency RC oscillator

This setting will only take effect when the selected oscillator is

powered up and stable. If the XOSC oscillator is not powered up, it

should be enabled by SLEEP.OSC_PD bit prior to selecting it as

souorce. Note that there is an additional wait time (64 µs) from

SLEEP.XOSC_STB

set until XOSC can be selected as source. If

RC osc is to be the source and it is powered down, setting this bit

will turn it on.

5:3

TICKSPD[2:0]

001

R/W

Timer ticks output setting, can not be higher than system clock

setting given by OSC bit setting

000 – 32 MHz

001 – 16 MHz

010 – 8 MHz

011 – 4 MHz

100 – 2 MHz

101 – 1 MHz

110 – 500 kHz

111 – 250 kHz

2:1

Reserved.

CLKSPD

Clock Speed. Indicates current system clock frequency. The value

of this bit is set by the OSC bit setting

0 – 32 MHz

1 – 16 MHz

This bit is updated when clock source selected with the OSC is

stable

13.1.5

Timer Tick generation

The power management controller generates

a tick or enable signal for the peripheral

timers, thus acting as a prescaler for the

timers. This is a global clock division for Timer

1, Timer 3 and Timer 4. The tick speed is

programmed from 0.25 MHz to 32 MHz in the

CLKCON.TICKSPD

that TICKSPD must not be set to a higher

frequency than system clock.

13.1.6

Data Retention

In power modes PM2 and PM3, power is

removed from most of the internal circuitry.

However parts of SRAM will retain its

contents. The content of internal registers is

also retained in PM2 and PM3.

The

XDATA

memory

locations

0xF000-

0xFFFF (4096 bytes) retains data in PM2 and

PM3. Please note the exception as given

below.

The XDATA memory locations 0xE000-

0xEFFF (4096 bytes) and the area 0xFD56-

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