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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST92163 датащи(PDF) 208 Page - STMicroelectronics |
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ST92163 датащи(HTML) 208 Page - STMicroelectronics |
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208 / 224 page  208/224 ST92163 - ELECTRICAL CHARACTERISTICS EXTERNAL INTERRUPT TIMING TABLE (VDD = 3.0 - 5.5V (1),T A =0°C+ 70°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. The value in the right hand two columns show the timing minimum and maximum for an internal clock at 24MHz (INTCLK). (1) 3.0 - 4.0V voltage range is only available on devices with suffix L or V, with different frequency limitatio ns (L: 8 MHz, V: 16 MHz) (2) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. EXTERNAL INTERRUPT TIMING N ° Symbol Parameter Value (Note) Unit Formula(2) Min Max 1 TwINTLR Low Level Pulse Width in Rising Edge Mode ≥ Tck+10 50 ns 2 TwINTHR High Level Pulse Width in Rising Edge Mode ≥ Tck+10 50 ns 3 TwINTHF High Level Pulse Width in Falling Edge Mode ≥ Tck+10 50 ns 4 TwINTLF Low Level Pulse Width in Falling Edge Mode ≥ Tck+10 50 ns |
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