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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST92163 датащи(PDF) 161 Page - STMicroelectronics |
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ST92163 датащи(HTML) 161 Page - STMicroelectronics |
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161 / 224 page  161/224 ST92163 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.9 Interrupts and DMA 8.4.9.1 Interrupts The SCI can generate interrupts as a result of sev- eral conditions. Receiver interrupts include data pending, receive errors (overrun, framing and par- ity), as well as address or break pending. Trans- mitter interrupts are software selectable for either Transmit Buffer Register Empty (BSN set) or for Transmit Shift Register Empty (BSN reset) condi- tions. Typical usage of the Interrupts generated by the SCI peripheral are illustrated in Figure 11. The SCI peripheral is able to generate interrupt re- quests as a result of a number of events, several of which share the same interrupt vector. It is therefore necessary to poll S_ISR, the Interrupt Status Register, in order to determine the active trigger. These bits should be reset by the program- mer during the Interrupt Service routine. The four major levels of interrupt are encoded in hardware to provide two bits of the interrupt vector register, allowing the position of the block of point- er vectors to be resolved to an 8 byte block size. The SCI interrupts have an internal priority struc- ture in order to resolve simultaneous events. Refer also to Section 0.1.3 for more details relating to Synchronous mode. Table 34. SCI Interrupt Internal Priority Receive DMA Request Highest Priority Transmit DMA Request Receive Interrupt Transmit Interrupt Lowest Priority |
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