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ST10R172L датащи(PDF) 38 Page - STMicroelectronics |
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ST10R172L датащи(HTML) 38 Page - STMicroelectronics |
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38 / 68 page ![]() 38/68 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.1 Cpu Clock Generation Mechanisms ST10R172L internal operation is controlled by the CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external timing (AC Characteristics) specification therefore depends on the time between two consec- utive edges of the CPU clock, called “TCL” (see figure below). The CPU clock signal can be generated by different mechanisms. The duration of TCLs and their variation (and also the external timing) depends on the fCPU generation mechanism. This must be considered when calculating ST10R172L timing. The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 11 CPU clock generation mechanisms P0.15-13 (P0H.7-5) CPU frequency fCPU = fXTAL * F External clock input range 10- 50MHz Notes 111 F XTAL * 4 2.5 to 12.5 MHz Default configuration 110 F XTAL * 3 3.33 to 16.66 MHz 101 F XTAL * 2 5 to 25 MHz Table 12 CPU clock generation mechanisms TCL TCL TCL TCL fCPU fXTAL fCPU fXTAL Phase Locked Loop Operation (PLL factor=4) Direct Clock Drive TCL TCL fCPU fXTAL Prescaler Operation 1 |
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