ST10R172L datasheet(16/68 Pages) STMICROELECTRONICS

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ST10R172L - INTERRUPT AND TRAP FUNCTIONS

5.2

Hardware traps

Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware

traps cause immediate non-maskable system reaction similar to a standard interrupt service

(branching to a dedicated vector table location). The occurrence of a hardware trap is

additionally signified by an individual bit in the trap flag register (TFR). Except when another

higher prioritized trap service is in progress, a hardware trap will interrupt any actual program

execution. In turn, hardware trap services can not normally be interrupted by standard or PEC

interrupts. The following table shows all of the possible exceptions or error conditions that can

arise during run-time:

Exception Condition

Trap Flag

Trap Vector

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

Hardware Reset

RESET

00’0000h

00h

III

Software Reset

RESET

00’0000h

00h

III

Watchdog Timer Overflow

RESET

00’0000h

00h

III

Class A Hardware Traps:

Non-Maskable Interrupt

NMI

NMITRAP

00’0008h

02h

Stack Overflow

STKOF

STOTRAP

00’0010h

04h

Stack Underflow

STKUF

STUTRAP

00’0018h

06h

Class B Hardware Traps:

Undefined opcode

UNDOPC

BTRAP

00’0028h

0Ah

Protected instruction fault

PRTFLT

BTRAP

00’0028h

0Ah

Illegal word operand access ILLOPA

BTRAP

00’0028h

0Ah

Illegal instruction access

ILLINA

BTRAP

00’0028h

0Ah

Illegal external bus access

ILLBUS

BTRAP

00’0028h

0Ah

Reserved

[2Ch – 3Ch][0Bh – 0Fh]

Software Traps

TRAP Instruction

Any [00’0000h

– 00’01FCh]

steps of 4h

Any

[00h – 7Fh]

Current

CPU

Priority

Table 3 Exceptions or error conditions

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