ADATE320 datasheet(16/78 Pages) AD

16 / 78 page

Data Sheet

ADATE320

SPECIFICATIONS

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Rev. C | 16 of 78

Table 7.

Parameter

Min

Typ

Max

Unit

Test Level

Test Conditions/Comments

Code 0x4000 (0.0 V) with PCHx at DAC Code 0xFFFF

(+7.5 V)

Offset TC, Voltage Clamps (PCHx/

PCLx)

±0.5

mV/°C

Gain, Voltage Clamps (PCHx/PCLx)

1.0

1.1

V/V

Range B, PPMU force ±0.5 mA into open; PCHx gain

derived from measurements at DAC Code 0x4000 (0.0

V) and DAC Code 0x8CCC (3.0 V) with PCLx at

DAC Code 0x0000 (−2.5 V); PCLx gain derived from

measurements at DAC Code 0x4000 (0.0 V) and DAC

Code 0x8CCC (3.0 V) with PCHx at DAC Code 0xFFFF

(7.5 V)

Gain TC, Voltage Clamps (PCHx/

PCLx)

±25

ppm/°C

INL, Voltage Clamps (PCHx/PCLx)

−20

+20

Range B, PPMU force ±0.5 mA into open after two-point

gain/offset calibration; measured over PPMU clamp

functional range

Positive Voltage Clamp, Voltage

Droop (Source)

−50

+50

∆V at DUTx pin, Range A, PCHx = +4.0 V, PCLx = −1.0

V, PPMU force 5.0 mA and 40 mA into open circuit,

calibrated

Negative Voltage Clamp, Voltage

Droop (Sink)

−50

+50

∆V at DUTx pin, Range A, PCHx = +4.0 V, PCLx = −1.0

V, PPMU force −5.0 mA and −40 mA into open circuit,

calibrated

DUTGND Voltage Accuracy

−5

±1

Over ±0.1 V range; measured at end points of clamp

functional range

PPMU CURRENT CLAMPS (FV)

PPMU enabled in FVMV, dc accuracy of the current

clamps only applies over the following conditions: 30%

FS ≤ PCHx ≤ 100% FS or −100% FS ≤ PCLx ≤ −30%

Functional Range

Low Current Clamp (PCLx)

−120

−20

%FS

For example, −120% FS in Range A is −48 mA and

−20% FS in Range A is −8 mA

High Current Clamp (PCHx)

120

%FS

For example, 20% FS in Range A is 8 mA and 120% FS

in Range A is 48 mA

DC Accuracy Range

Low Current Clamp (PCLx)

−100

−30

%FS

For example, −100% FS in Range A is −40 mA and

−30% FS in Range A is −12 mA

High Current Clamp (PCHx)

100

%FS

For example, 30% FS in Range A is 12 mA and 100%

FS in Range A is 40 mA

Static Current Limit, Source and Sink,

All Ranges

±120

±140

±160

%FS

PCLx at DAC Code 0x0000 (−2.5 V), PCHx at DAC

Code 0xFFFF (7.5 V), sink: force −1.5 V, short DUTx to

4.5 V, source: force 4.5 V, short DUTX to −1.5 V

Offset, Current Clamps (PCHx/PCLx) −10

+10

%FSR

All ranges; PPMU force ±1.0 V into 0.0 V1

Offset TC, Current Clamps (PCHx/

PCLx)

±0.02

%FSR/°C

All ranges

Gain Error, Current Clamps (PCHx/

PCLx)

All ranges; PPMU force ±1.0 V into 0.0 V2

Gain TC, Current Clamps (PCHx/

PCLx)

±50

ppm/°C

All ranges

INL, Current Clamps (PCHx/PCLx)

−0.15

+0.15

%FSR

All ranges; PPMU force ±1.0 V into 0.0 V, after two-point

gain/offset calibration; PCHx calibration at DAC Code

0xA000 (3.75 V or 50% FS) and DAC Code 0xB333

(4.50 V or 80% FS); PCLx calibration at DAC Code

0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC

(0.50 V or −80% FS); measured over dc accuracy range

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