ADUCM320BBCZ datasheet(7/31 Pages) AD

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ADuCM320

Data Sheet

Rev. C | Page 6 of 30

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Leakage Current

AIN0 to AIN4, AIN6 to AIN15

±1.5

AIN5

±20

Pin shared with comparator

Input Current

±9

μA/V

At 1 MSPS; buffer off

±6

μA/V

≤800 kSPS; buffer off

±4

μA/V

500 kSPS; buffer off;

ADCCNVC[25:16] = 0x1E

Input Capacitance

During ADC acquisition

ADC INPUT BUFFER2

When enabled by software

Voltage Compliance1

0.15

2.5

Reduced accuracy below 0.15 V

Input Current

±100

VIN = 0.15 V to 2.5 V, ADC converting

ON-CHIP VOLTAGE REFERENCE

2.51

0.47 μF from VREF_1V2 to AGND4;

reference is measured with all

ADCs, VDACs, and IDACs enabled

Accuracy

±5

TA = 25°C

Reference Temperature Coefficient1

−34

−15

ppm/°C

Power Supply Rejection Ratio

PSRR

Internal VREF Power-On Time

EXTERNAL REFERENCE INPUT

Range1

1.8

2.5

ADC

Input Current

200

μA

BUFFERED REFFERNCE OUTPUT

Output Voltage

2.504

Accuracy

±8

TA = 25°C, load = 1.2 mA

Reference Temperature Coefficient1

−55

−5

+40

μV/°C

100 nF from BUF_VREF2V5 to

AGND4

Output Impedance

TA = 25°C

Load Current1

1.2

VDAC CHANNEL SPECIFICATIONS

RL = 5 kΩ, CL = 100 pF3

DC Accuracy1

Bits

1 LSB = 2.5 V/212

Resolution1

Bits

Number of data bits

Relative Accuracy4

INL

±4

LSB

1 LSB = 2.5 V/212

Differential Nonlinearity4

DNL

−0.99

LSB

Guaranteed monotonic, 1 LSB =

2.5 V/212

Offset Error

±3

±15

2.5 V internal reference, DAC

Output Code 0

Drift

±13

μV/°C

Gain Error5

±0.3

±0.85

0 V to internal VREF range

±0.4

±1

0 V to AVDD range

Drift

6.5

ppm/°C

Excluding reference drift

Mismatch

0.1

% of full scale on DAC0

Analog Outputs

Output Voltage Range 11

0.15

2.5

Output Voltage Range 21

0.15

AVDDx− 0.15

Output Impedance

DAC AC Characteristics

Output Settling Time

μs

Settled to ±1 LSB

Glitch Energy

±20

nV-sec

1 LSB change when the maximum

number of bits changes

simultaneously in the

DACxDAT register

IDAC CHANNEL SPECIFICATIONS

Resolution1

Bits

Combination of overlapping

11 bits and 5 bits

Full-Scale Output1

150

Supply Voltage Each Channel1

1.8

2.5

Separate PVDDx supply for each

channel

Output Compliance Range

IDAC0, IDAC1

0.4

PVDDx − 400 mV

See Figure 11

IDAC2, IDAC3

0.4

PVDDx − 250 mV

See Figure 11

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