CS5543 datasheet(19/30 Pages) CIRRUS

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CS5542 CS5543

DS109PP2

CLKIN. FRAME will be latched into the CS5543

by the rising edge of CLKIN. This will subse-

quently generate an FSYNC signal to synchronize

the CS5542 modulators.

System Connections

An eight channel digitizer system can be construct-

ed using four CS5542 dual modulators with one

CS5543 eight-channel decimator. Figure 2 illus-

trates the hardware signal connections for an eight

channel system.

Digitizer blocks of eight channels each can be cas-

caded to connect 128 blocks together for a total of

1024 digitizer channels. All clocks in the system

are related to the CLKIN master clock. Assuming

that CLKIN= 2.048 MHz, the converter output

word rate will be CLKIN/2048. A data framing

signal, FRAME, synchronizes the digital output

data and the modulator data. The FRAME signal

must occur at the output word rate. The DATA-

CLK must be three times faster than the CLKIN

rate, 6.144 MHz in this example.

The CS5543 has four DATAOUT lines. Each of

the lines provides an output for the data from two

of the eight channels associated with a single

CS5543. Data from any one DATAOUT line is se-

rially transferred out of the DATAOUT pin in 48-

bit blocks, consisting of two 24-bit words.

With 128 CS5543 linked together, each of the four

serial lines linking DATAOUT pins to DATAIN

pins is in effect a serial shift register 6144 (48 X

128) bits long. The DATACLK is used to shift data

out of each CS5543 in 48 bit blocks. For a 1024

channel system with an CLKIN rate of 2.048 MHz,

the 6.144 MHz DATACLK will shift out the data

for all 1024 channels in one millisecond.

Analog Input

The CS5542 modulator is optimized to be driven

by a photodiode current source. Photodiodes have

large output impedances. A photodiode also has a

capacitance which is a function of its size. The

CS5542 relies on this capacitance to ensure the sta-

bility of its input stage. The capacitance also af-

fects the bandwidth of the input circuit.

In all cases the modulator assumes that the external

shunt capacitance of the photodiode is at least

220pF.

If the input source is actually a voltage source and

a resistor is used to generate the input current, a 220

pF capacitor should be connected between the in-

put pin and ground. The resistor will add additional

current noise into the circuit and will degrade the

dynamic range somewhat.

Voltage Reference

The voltages supplied to the VREF+ and VREF-

pins can range from ±2.0 volts to ±4.1 volts with

±4. 0 volts being preferred. VREF+ and VREF-

voltages should be balanced and have low noise.

Figure 7 illustrates how a bandgap voltage refer-

ence can be well filtered to provide a low noise

source for +4.0 volts.

>9V

µF

LT1019-

4.02K

10K

100

µF

100

µF

>9V

OP27

47K

0.01

µF

+ 15µF + 0.1µF

+4.0

Figure 7. Noise-Filtered Bandgap Reference

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