Busy flag

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When the Busy flag is logical 1, the SBN1661G_M18-D series is executing its internal

operations.

Any command other than Status Read is rejected during this time. The Busy

flag is output at pin D7 by the Status Read command.

If an appropriate cycle time (tCYC)

is given, this flag needs not be checked at the beginning of each command and, therefore,

the MPU processing capacity can greatly be enhanced.

Display

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Start Line and Line Count Registers

The contents of this register form a pointer to a line of data in display data RAM

corresponding to the first line of the display (COM0), and are set by the Display Start Line

command.

Column Address Counter

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The column address counter is a 7-bit presettable counter that supplies the column

address for MPU access to the display data RAM.

See Figure 1.

The counter is

incremented by one every time the driver receives a Read or Write Display Data command.

Addresses above 50H are invalid, and the counter will not increment past this value.

The

contents of the column address counter are set with the Set Column Address command.

Display Data RAM

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The display data RAM stores the LCD display data, on a 1-bit per pixel basis.

The

relation-ship between display data, display address and the display is shown in Figure 1.

Page Register

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The page register is a 2-bit register that supplies the page address for MPU access to the

display data RAM.

See the follow Figure. The contents of the page register are set by

the Set Page Register command.

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