WM8951L datasheet(21/42 Pages) WOLFSON

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Production Data

WM8951

PD Rev 4.1 December 2007

XTI/MCLK

XTO

DGND

Figure 16 Crystal Oscillator Application Circuit

The WM8951L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a

requirement for high quality audio ADCs, regardless of the converter architecture. The WM8951L

architecture is less susceptible than most converter techniques but still requires clocks with less than

approximately 1ns of jitter to maintain performance. In applications where there is more than one

source for the master clock, it is recommended that the clock is generated by the WM8951L to

minimise such problems.

CLOCKOUT

The Core Clock is internally buffered and made available externally to the audio system on the

CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for

driving external loads.

There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will

inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to

Electrical Characteristics.

CLKOUT can also be divided by 2 under software control, refer to Table 8. Note that if CLKOUT is

not required then the CLKOUT buffer on the WM8951L can be safely powered down to conserve

power (see POWER DOWN section). If the system architect has the choice between using FCLKOUT =

FMCLK or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the

divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical

Characteristics for timing information.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001000

Sampling

Control

CLKODIV2

CLKOUT divider select

1 = CLOCKOUT is Core Clock

divided by 2

0 = CLOCKOUT is Core Clock

Table 8 Programming CLKOUT

CLKOUT is disabled and set low whenever the device is in reset.

DIGITAL AUDIO INTERFACES

WM8951L may be operated in either one of the 4 offered audio interface modes. These are:

•

Right justified

•

Left justified

•

I2S

•

DSP mode

All four of these modes are MSB first and operate with data 16 to 32 bits.

Note that 32 bit data is not supported in right justified mode.

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