AD5544ARS datasheet(7/20 Pages) AD

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AD5544/AD5554

Rev. A | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5544/

AD5554

TOP VIEW

(Not to Scale)

AGNDA

AGNDD

IOUTA

IOUTD

VREFA

VREFD

RFBARFBD

MSB

DGND

VSS

VDD

AGNDF

CLK

SDO

SDI

RFBB

RFBC

VREFB

VREFC

IOUTB

IOUTC

AGNDBAGNDC

NC = NO CONNECT

LDAC

Figure 3. AD5544/AD5554 Pin Configuration

Table 4. Pin Function Descriptions

No.

Name

Function

AGNDA

DAC A Analog Ground.

IOUTA

DAC A Current Output.

VREFA

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.

RFBA

Establish voltage output for DAC A by connecting to external amplifier output.

MSB

MSB Bit. Set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD.

Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544

and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0.

VDD

Positive Power Supply Input. Specified range of operation 5 V ±10%.

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input

CLK

Clock Input. Positive edge clocks data into shift register.

SDI

Serial Data Input. Input data loads directly into the shift register.

RFBB

Establish voltage output for DAC B by connecting to external amplifier output.

VREFB

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.

IOUTB

DAC B Current Output.

AGNDB

DAC B Analog Ground.

AGNDC

DAC C Analog Ground.

IOUTC

DAC C Current Output.

VREFC

DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.

RFBC

Establish voltage output for DAC C by connecting to external amplifier output.

No Connect. Leave pin unconnected.

SDO

Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544

and 17 clock pulses for AD5554 after input at the SDI pin.

LDAC

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous

active low input. See Table 5 and Table 6 for operation.

AGNDF

High Current Analog Force Ground.

VSS

Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.

DGND

Digital Ground Pin.

RFBD

Establish Voltage Output for DAC D by Connecting to External Amplifier Output.

VREFD

DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.

IOUTD

DAC D Current Output.

AGNDD

DAC D Analog Ground.

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