AD5544ARS datasheet(5/20 Pages) AD

5 / 20 page

AD5544/AD5554

Rev. A | Page 5 of 20

Parameter

Symbol

Condition

Min

Typ

Max

Unit

INTERFACE TIMING2, 3

Clock Width High

tCH

Clock Width Low

tCL

CS to Clock Setup

tCSS

Clock to CS Hold

tCSH

Clock to SDO Prop Delay

tPD

Load DAC Pulse Width

tLDAC

Data Setup

tDS

Data Hold

tDH

Load Setup

tLDS

Load Hold

tLDH

SUPPLY CHARACTERISTICS

Power Supply Range

VDD RANGE

4.5

5.5

Positive Supply Current

IDD

Logic inputs = 0 V

250

µA

Negative Supply Current

ISS

Logic inputs = 0 V, VSS = –5 V

0.001

µA

Power Dissipation

PDISS

Logic inputs = 0 V

1.25

Power Supply Sensitivity

PSS

∆VDD = ±5%

0.006

%/%

AC CHARACTERISTICS4

Output Voltage Settling Time

To ±0.1% of full scale, data = 0000H to 3FFFH to 0000H

µs

Output Voltage Settling Time

To ±0.0015% of full scale, data = 0000H to 3FFFH

to 0000H

µs

Reference Multiplying BW

BW – 3 dB

VREFX = 100 mV rms, data = 3FFFH, CFB = 15 pF

MHz

DAC Glitch Impulse

VREFX = 10 V, data 0000H to 2000H to 0000H

nV-s

Feedthrough Error

VOUTX/VREFX

Data = 0000H, VREFX = 100 mV rms, f = 100 kHz

–65

Crosstalk Error

VOUTA/VREFB

Data = 0000H, VREFB = 100 mV rms, adjacent channel,

f = 100 kHz

–90

Digital Feedthrough

CS = 1, and fCLK = 1 MHz

nV-s

Total Harmonic Distortion

THD

VREF= 5 V p-p, data = 3FFFH, f = 1 kHz

–90

Output Spot Noise Voltage

f = 1 kHz, BW = 1 Hz

nV√Hz

1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 RFB terminal is

tied to the amplifier output. Typical values represent average readings measured at 25°C.

2 These parameters are guaranteed by design and not subject to production testing.

3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

4 All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.

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