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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD913F2 датащи(PDF) 73 Page - STMicroelectronics |
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PSD913F2 датащи(HTML) 73 Page - STMicroelectronics |
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73 / 94 page  Preliminary Information PSD9XX Family 69 -70 -90 -15 Symbol Parameter Conditions Min Max Min Max Min Max Unit tLVLX ALE or AS Pulse Width 15 20 28 tAVLX Address Setup Time (Note 1) 4 6 10 ns tLXAX Address Hold Time (Note 1) 7 8 11 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 8 15 20 ns t SLWL CS Valid to Leading Edge of WR (Note 3) 12 15 20 ns t DVWH WR Data Setup Time (Note 3) 25 35 45 ns t WHDX WR Data Hold Time (Note 3) 4 5 5 ns t WLWH WR Pulse Width (Note 3) 31 35 45 ns tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 6 8 10 ns tWHAX2 Trailing Edge of WR to DPLD Address Input Invalid (Note 3 and 4) 0 0 0 ns tWHPV Trailing Edge of WR to Port Output Valid Using I/O Port Data Register (Note 3) 27 30 38 ns tAVPV Address Input Valid to Address (Note 2) 20 25 30 ns Output Delay Write Timing (5 V ± 10% Versions) Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) NOTES: 1. Any input used to select an internal PSD9XX function. 2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. 4. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. -70 -90 -15 Fast Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Min Max Aloc OFF (Note 1) Unit tPD PLD Input Pin/Feedback to PLD Combinatorial 20 25 32 Add 2 Add 10 Sub 2 ns Output tARD PLD Array Delay Any 11 16 22 Add 2 ns Micro ⇔Cell PLD Combinatorial Timing (5 V ± 10%) NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0]. |
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