MK68901 datasheet(22/33 Pages) STMICROELECTRONICS

22 / 33 page

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC = 5.0Vdc ± 5%, GND = 0Vdc, TA =0°Cto 70°C)

Val ue

MK689 01-4

MK689 01-5

Number

Characteristic

Min.

Max.

Min.

Max.

Unit

Fi g.

Note

Timer Clock High Time

110

Timer Clock Cycle Time

250

1000

200

1000

RESET Low Time

1.8

µs30

Delay to Falling INTR from External Interrupt

Active Transition

380

Transmitter Internal Interrupt Delay from Falling

Edge of TC

550

Receiver Buffer Full Interrupt Transition Delay

from Rising Edge of RC

800

Receiver Error Interrupt Transition Delay from

Falling Edge of RC

800

Serial in Set Up Time to Rising Edge of RC

(divide by one only)

Data Hold Time from Rising Edge of RC

(divide by one only)

350

325

Serial Output Data Valid from Falling Edge of TC

(

÷1)

440

420

Transmitter Clock Low Time

500

450

Transmitter Clock High Time

500

450

Transmitter Clock Cycle Time

1.05

∞

0.95

∞

µs28

Receiver Clock Low Time

500

450

Receiver Clock High Time

500

450

Receiver Clock Cycle Time

1.05

∞

0.95

∞

µs27

CS, IACK, DS Width Low

T CL K

Serial Output Data Valid from Falling Edge of TC

(

÷16)

490

370

Notes :

1. IEO only goes low if no acknowledgeable interrupt is

pending. If IEO goes low, DTACK and the data bus re-

main tri-stated.

2. TCLK refers to the clock applied to the MFP CLK input

pin. tCLK refers to the timer clock signal, regardless of

whether that signal comes from the XTAL 1/XTAL2crys-

tal clock inputs or the TAI or TBI timer inputs.

3. If the setup time is not met, CS or IACK will not be reco-

gnized until the next falling CLK.

4. If this setup time is met (for consecutive cycles), the mi-

nimum hold-off time of one clock cycle will be obtained.

If not met, the hold-off will be two clock cycles.

5. CS is latched internally, therefore if spec’s 1 and 24 are

met then CS may be reasserted before the rising clock

and still terminate the current bus cycle.The new bus cy-

cle will be delayed by the MK68901 until all appropriate

internal operations have completed.

6. Although CS and DTACK are synchronized with the

clock, the data out during a read cycle is asynchronous

to the clock, relying only on CS for timing.

7. Spec. 30 applies to timer outputs TAO and TBO only.

MK68901

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