MK68901 datasheet(17/33 Pages) STMICROELECTRONICS

17 / 33 page

TRANSMITTER

The transmitter section of the USART is configured

as to format, word length, etc. by the UCR, as pre-

viously described. The status of the transmitter can

be determined by reading or writing the Transmitter

Status Register (TSR). The TRS is configured as fol-

lows :

BE :

Buffer Empty. This status bit is set when

the word in the transmit buffer is transfer-

red to the output shift register and thus

the transmit buffer may be reloaded with

the next data word. The flag is cleared

when the transmit buffer is reloaded. The

transmit buffer is loaded by writing to the

UDR.

UE :

This bit is set when the last word has

been shifted out of the transmit shift re-

gister before a new word has been loa-

ded into the transmit buffer. It is not ne-

cessary to clear this bit before loading the

UDR.

This bit may be cleared by either reading

the TSR or by disabling the transmitter.

After the setting of the UE bit, one full

transmitter clock cycle is required before

this bit can be cleared by a read. The ti-

ming in some systems may allow a read

of the TSR before the required clock cy-

cle has been completed. This would re-

sult in the UE bit not being cleared until

the following read. To avoid this problem,

a dummy read of the TSR should be per-

formed at the end of he UE service rou-

tine.

Only one underrun error may be genera-

ted between loads of the UDR regardless

of the number of transmitter clock cycles

between UDR loads.

AT :

This bit causes the receiver to be enabled

at the end of the transmission of the last

word in the transmitter if the transmitter

has been disabled.

END :

End or Transmission. When the transmit-

ter is turned off with a character still in the

output shift register, transmission will

continue until that character is shifted

out. Once it has cleared the output regis-

ter, the END bit will be set. If no character

is being transmitted when the transmitter

is disabled, the transmitter will stop at the

next rising edge of the internal shift clock,

and END will immediately be set. The

END bit is cleared by re-enabling the

transmitter.

B :

Break. This control bit will cause a break

to be transmitted. When a ”1” is written to

the B bit of the TSR, a break will be trans-

mitted upon completion of the character

(if any) currently being transmitted. A

break will continue to be transmitted until

the B bit is cleared by writing a ”0” tot his

bit of the TSR. At that time, normal trans-

mission will resume. The B bit has no

function in the synchronous format. Set-

ting the ”B” bit to a one keeps the ”BE” bit

from being set to a one. So, if there were

a word in the buffer at the start of break,

it would remain there until the end of

break, at which time it would be transmit-

ted (if the transmitter is still enabled). If

the buffer were not full at the start of

break, it could be written at any time du-

ring the break. If the buffer is empty at the

end of break, the underrun flag will be set

(unless the transmitter is disabled).

The BREAK bit cannot be set until the

transmitter has been enabled and the

transmitter has had sufficient time (one

clock cycle) to perform the internal reset

and initialization functions.

H,L :

High and Low. These two control bits are

used to configure the transmitter output,

when the transmitter is disabled, as fol-

lows :

H L Output State

0 0 Hi-Z

0 1 Low (”0”)

1 0 High

1 1 Loop-Connects transmitter output to

receiver input, and TC to Receiver Clock

(RC and SI are not used ; they are bypas-

sed internally). In loop back mode, trans-

mitter output goes high when disabled.

Altering these two bits after Transmitter

MK68901

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