WM8959 datasheet(19/155 Pages) WOLFSON

19 / 155 page

Pre-Production

WM8959

PP, May 2008, Rev 3.1

Test Conditions

DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25

oC, 1kHz signal, fs = 48kHz,

PGA gain = 0dB, 24-bit audio data unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analogue Reference Levels

VMID Midrail Reference Voltage

-3%

AVDD/2

+3%

Microphone Bias

3mA load current

M1BSEL=0 / M2BSEL=0

-5%

0.9

×AVDD

+5%

Bias Voltage

3mA load current

M1BSEL=1 / M2BSEL=1

-5%

0.65

×AVDD

+5%

Bias Current Source

Output Noise Density

1kHz to 20kHz

100

nV/

√Hz

AVDD PSRR (217Hz)

100mV pk-pk @217Hz

on AVDD

Digital Input / Output

Input HIGH Level

0.7

×DBVDD

Input LOW Level

0.3

×DBVDD

Note that digital input pins should not be left unconnected / floating.

Internal pull-up/pull-down resistors may be enabled on GPIO1, GPIO3, GPIO4 and GPIO5 if required.

Output HIGH Level

IOL=1mA

0.9

×DBVDD

Output LOW Level

IOH=-1mA

0.1

×DBVDD

H10

Input capacitance

H11

Input leakage

-0.9

0.9

PLL

PRESCALE = 0b

MHz

H12

Input Frequency

PRESCALE = 1b

MHz

H13

Lock time

200

GPIO

SYSCLK=MCLK;

OPCLKDIV=0000

SYSCLK=MCLK;

OPCLKDIV=1000

SYSCLK=PLL output;

OPCLKDIV=0000

H14

Clock output duty cycle

(Integer OPCLKDIV)

SYSCLK=PLL output;

OPCLKDIV=1000

SYSCLK=MCLK;

OPCLKDIV=0100

H15

Clock output duty cycle

(Non-integer OPCLKDIV)

SYSCLK=PLL output;

OPCLKDIV=0100

Input de-bounced

221 / fSYSCLK

222 / fSYSCLK

Input de-bounced

TOCLKSEL=1

219 / fSYSCLK

220 / fSYSCLK

H16

Interrupt response time for accessory /

button detect

Input not de-bounced

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