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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS7343L датащи(PDF) 30 Page - ams-OSRAM AG |
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AS7343L датащи(HTML) 30 Page - ams-OSRAM AG |
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30 / 53 page  Document Feedback AS7343L Register Description Datasheet • PUBLIC DS001038 • v2-00 • 2022-Aug-12 52 │ 29 10.2.3 ADC Configuration The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to adjust the gain and setup the auto zero compensation for the ADCs. CFG1 Register (Address 0xC6) Figure 29: CFG1 Register Addr: 0xC6 CFG1 Bit Bit Name Default Access Bit Description 7:5 Reserved 0 Reserved 4:0 AGAIN 9 RW Spectral Engines Gain Setting. Sets the spectral sensitivity. VALUE GAIN 0 0.5x 1 1x 2 2x 3 4x 4 8x 5 16x 6 32x 7 64x 8 128x 9 256x 10 512x 11 1024x 12 2048x AZ_CONFIG Register (Address 0xDE) The following register configures how often the spectral engine offsets are reset (auto zero) to compensate for changes of the device temperature. The typical time auto zero needs to be completed is 15 ms. |
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