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M68AW512D

Write Mode

The M68AW512D, when Chip Select (E2) is High,

is in the Write Mode whenever the W and E1 are

Low. Either the Chip Enable Input (E1) or the Write

Enable input (W) must be de-asserted during Ad-

dress transitions for subsequent write cycles.

When E1 or W is Low, and UB or LB is Low, write

cycle begins on the W or E1 falling edge. When E1

and W are Low, and UB = LB = High, write cycle

begins on the first falling edge of UB or LB. There-

fore, address setup time is referenced to Write En-

occurring falling edge.

The Write cycle can be terminated by the earlier

rising edge of E1, W, UB and LB.

If the Output is enabled (E1 = Low, E2 = High, G =

Low, LB or UB = Low), then W will return the out-

edge. Care must be taken to avoid bus contention

in this type of operation. Data input must be valid

Figure 10. Write Enable Controlled, Write AC Waveforms

Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.

AI05982

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A18

E1

W

DQ0-DQ15

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

tBLBH

UB, LB

E2

tELWH