поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

STM32F103ZC датащи(PDF) 94 Page - STMicroelectronics

номер детали STM32F103ZC
подробное описание детали  Performance line, ARM-based 32-bit MCU with up to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces
PDF  118 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103ZC датащи(HTML) 94 Page - STMicroelectronics

Back Button STM32F103ZC Datasheet HTML 90Page - STMicroelectronics STM32F103ZC Datasheet HTML 91Page - STMicroelectronics STM32F103ZC Datasheet HTML 92Page - STMicroelectronics STM32F103ZC Datasheet HTML 93Page - STMicroelectronics STM32F103ZC Datasheet HTML 94Page - STMicroelectronics STM32F103ZC Datasheet HTML 95Page - STMicroelectronics STM32F103ZC Datasheet HTML 96Page - STMicroelectronics STM32F103ZC Datasheet HTML 97Page - STMicroelectronics STM32F103ZC Datasheet HTML 98Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 94 / 118 page
background image
Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
94/118
Table 52.
I2S characteristics (1)
1.
TBD = to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fCK
1/tc(CK)
I2S clock frequency
Master
TBD
TBD
MHz
Slave
0
TBD
tr(CK)
tf(CK)
I2S clock rise and fall time
capacitive load
CL = 50 pF
TBD
ns
tv(WS)
(2)
2.
Data based on design simulation and/or characterization results, not tested in production.
WS valid time
Master
TBD
th(WS)
(2)
WS hold time
Master
TBD
tsu(WS)
(2)
WS setup time
Slave
TBD
th(WS)
(2)
WS hold time
Slave
TBD
tw(CKH)
(2)
tw(CKL)
(2)
CK high and low time
Master fPCLK= TBD,
presc = TBD
TBD
tsu(SD_MR)
(2)
tsu(SD_SR)
(2)
Data input setup time
Master receiver
Slave receiver
TBD
TBD
th(SD_MR)
(2)(3)
th(SD_SR)
(2)(3)
3.
Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
Data input hold time
Master receiver
Slave receiver
TBD
TBD
th(SD_MR)
(2)
th(SD_SR)
(2)
Data input hold time
Master fPCLK = TBD
Slave fPCLK = TBD
TBD
TBD
tv(SD_ST)
(2)(3)
Data output valid time
Slave transmitter
(after enable edge)
TBD
fPCLK = TBD
TBD
th(SD_ST)
(2)
Data output hold time
Slave transmitter
(after enable edge)
TBD
tv(SD_MT)
(2)(3)
Data output valid time
Master transmitter
(after enable edge)
TBD
fPCLK = TBD
TBD
TBD
th(SD_MT)
(2)
Data output hold time
Master transmitter
(after enable edge)
TBD



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com