LXT9782 datasheet(6/78 Pages) INTEL

6 / 78 page

LXT9762/9782 — Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII

Datasheet

Tables

LXT97x2 Serial MII Signal Descriptions.............................................................. 13

LXT97x2 Signal Detect/TP Select Signal Descriptions ....................................... 14

LXT97x2 Network Interface Signal Descriptions................................................. 14

LXT97x2 JTAG Test Signal Descriptions ............................................................ 15

LXT97x2 Miscellaneous Signal Descriptions ...................................................... 15

LXT97x2 Power Supply Signal Descriptions....................................................... 16

LXT97x2 LED Signal Descriptions ...................................................................... 17

Unused Pins........................................................................................................ 19

Hardware Configuration Settings ........................................................................ 27

SMII Signal Summary ......................................................................................... 30

RX Status Encoding Bit Definitions ..................................................................... 33

4B/5B Coding ...................................................................................................... 36

BSR Mode of Operation ...................................................................................... 45

Supported JTAG Instructions .............................................................................. 45

Device ID Register .............................................................................................. 45

Magnetics Requirements .................................................................................... 48

Absolute Maximum Ratings ................................................................................ 53

Operating Conditions .......................................................................................... 53

Digital I/O Characteristics 1................................................................................. 54

Digital I/O Characteristics - SMII Pins ................................................................. 54

Required REFCLK and SYNC Characteristics.................................................... 54

100BASE-TX Transceiver Characteristics .......................................................... 55

100BASE-FX Transceiver Characteristics .......................................................... 55

10BASE-T Transceiver Characteristics............................................................... 55

MII Sync Timing Parameters ............................................................................... 56

100BASE-TX Receive Timing Parameters ......................................................... 56

100BASE-TX Transmit Timing Parameters ........................................................ 57

100BASE-FX Receive Timing Parameters ......................................................... 58

100BASE-FX Transmit Timing Parameters ........................................................ 58

10BASE-T Receive Timing Parameters.............................................................. 59

10BASE-T Transmit Timing Parameters............................................................. 59

Auto-Negotiation and Fast Link Pulse Timing Parameters ................................. 60

MDIO Timing Parameters ................................................................................... 61

Power-Up Timing Parameters............................................................................ 62

Reset and Power-Down Recovery Timing Parameters....................................... 62

Control Register (Address 0)............................................................................... 66

Status Register (Address 1) ................................................................................ 66

PHY Identification Register 1 (Address 2)........................................................... 67

PHY Identification Register 2 (Address 3)........................................................... 68

Auto-Negotiation Advertisement Register (Address 4) ....................................... 68

Auto-Negotiation Link Partner Base Page Ability Register (Address 5) .............. 69

Auto-Negotiation Expansion (Address 6) ............................................................ 70

Auto-Negotiation Next Page Transmit Register (Address 7)............................... 71

Auto-Negotiation Link Partner Next Page Receive Register (Address 8) ........... 71

Port Configuration Register (Address 16, Hex 10) .............................................. 72

Quick Status Register (Address 17, Hex 11) ...................................................... 72

Interrupt Enable Register (Address 18, Hex 12) ................................................. 73

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