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LXT9782 датащи(PDF) 13 Page - Intel Corporation |
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LXT9782 датащи(HTML) 13 Page - Intel Corporation |
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13 / 78 page ![]() Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782 Datasheet 13 Table 1. LXT97x2 Serial MII Signal Descriptions 9762 Pin# 9782 Pin# Symbol Type1 Signal Description2, 3 PQFP PQFP PBGA Serial MII Data Interface Pins 59 59 W4 TXD0 I Transmit Data - Ports 0-7. These serial input streams provide data to be transmitted to the network. LXT97x2 clocks the data in synchronously to REFCLK. 54 54 V2 TXD1 37 37 N4 TXD2 17 30 L3 TXD3 822 J2 TXD4 317 G2 TXD5 – 8D4 TXD6 – 3C2 TXD7 60 60 V5 RXD0 O Receive Data - Ports 0-7. These serial output streams provide data received from the network. LXT97x2 drives the data out synchronously to REFCLK. 55 55 W2 RXD1 38 38 P2 RXD2 18 33 M2 RXD3 923 K1 RXD4 418 H2 RXD5 – 9E2 RXD6 – 4C3 RXD7 90 90 W14 SYNC I SMII Synchronization. The MAC must generate a SYNC pulse every 10 REFCLK cycles to synchronize the SMII. 92 92 Y15 REFCLK I Reference Clock. The LXT97x2 requires a 125 MHz SMII reference clock input at this pin. Refer to Functional Description for detailed clock requirements. MII Control Interface Pins 3 71 71 W8 MDIO I/O Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. 84 84 U12 MDINT OD Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin indicates status change. 70 70 V8 MDC I Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. 85 85 Y12 MDDIS I Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations. When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only the initial or “default” values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain. 2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762. 3. The LXT97x2 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15). |
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