TMS320DM647_0804 datasheet(113/182 Pages) TI

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AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/

ABA[1:0]

AED[15:0]

AAOEASOE

AR/W

AAWEASWE

AARDY

ByteEnables

Address

ReadData

Hold=1

Strobe=4

Setup=1

DEASSERTED

AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/ABA[1:0]

AED[15:0]

ASADSASRE

AAOEASOE

AAWEASWE

BE1

BE2

BE3

BE4

EA1

EA2

EA3

EA4

TMS320DM647/TMS320DM648

Digital Media Processor

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SPRS372B – MAY 2007 – REVISED APRIL 2008

Figure 6-25. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)

NOTE

This information applies to Figure 6-26 and Figure 6-27.

The following parameters are programmable via the EMIF Chip Select n Configuration

• Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency

• Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

• ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface,

ACEx goes inactive after the final command has been issued (CE_EXT = 0). For

synchronous FIFO interface, ACEx is active when AAOE/ASOE is active (CE_EXT =

1).

• Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM

interface, ASADS/ASRE has deselect cycles (R_ENABLE = 0). For FIFO interface,

ASADS/ASRE has NO deselect cycles (R_ENABLE = 1).

In this figure, W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

Figure 6-26. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)

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