TMS320DM647_0804 datasheet(87/182 Pages) TI

87 / 182 page

TMS320DM647/TMS320DM648

Digital Media Processor

www.ti.com

SPRS372B – MAY 2007 – REVISED APRIL 2008

Table 6-23. Timing Requirements for Reset(1)(2) (see Figure 6-10 and Figure 6-11)

720

900

NO.

UNIT

MIN

MAX

tw(POR)

Pulse duration, POR low(3)

128D

tw(RESET)

Pulse duration, RESET low

24D

Setup time, boot mode and configuration pins valid before POR high or RESET

tsu(boot)

high(4)(5)

Hold time, boot mode and configuration pins valid after POR high or RESET

th(boot)

high(4)(5)

(1)

C = 1/CLKIN1 clock frequency in ns

(2)

D = 1/CLKIN2 clock frequency in ns

(3)

If CLKIN2 is not used, tw(POR) must be measured in terms of CLKIN1 cycles; otherwise, use the slower of the CLKIN1,CLKIN2 cycles.

(4)

AEA[22:11], and UHPIEN are the boot configuration pins during device reset.

(5)

P = 1/CPU clock frequency in nanoseconds

Table 6-24. Switching Characteristics Over Recommended Operating Conditions During Reset(1)

(see Figure 6-11)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

td(PORH-RSTATH)

Delay time, POR high AND RESET high to RESETSTAT high

1500C

(1)

C = 1/CLKIN1 clock frequency in ns.

For Figure 6-10, note the following:

• Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high

impedance as soon as their respective power supply has reached normal operating conditions. Pins

remain in high impedance until configured otherwise by their respective peripherals.

• Low group consists of pins that become low as soon as their respective power supply has reached

normal operating conditions. Pins remain low until configured otherwise by their respective peripheral.

• High group consists of pins that become high as soon as their respective power supply has reached

normal operating conditions. Pins remain high until configured otherwise by their respective peripheral.

• All peripherals must be enabled through software following a power-on reset; for more details, see

Section 6.7.1, Power-on Reset.

• For power-supply sequence requirements, see Section 6.3.1.

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